1. Field of the Invention
The present invention relates to a semiconductor package.
2. Description of the Related Art
An increasing demand for miniaturization of electrical/electronic products with high performance has motivated research and development on technologies for the manufacture of large-capacity semiconductor modules. For example, a semiconductor module with large capacity may be manufactured by an increase in the capacity (that is, high integration) of constituent memory chips. This high integration may be realized by integrating a larger number of cells in a defined space of the semiconductor chips.
High integration of memory chips needs highly advanced technologies, for example, a technology associated with precise and fine line widths, and requires much development time. Under these circumstances, a semiconductor die stacking technology has been proposed to provide large-capacity semiconductor modules. Another technology has been proposed for fabricating next-generation wafer-level packages in which a plurality of semiconductor dies are formed.
In the fabrication of a wafer-level semiconductor package, via holes are formed in semiconductor chips and a solder is filled in the via holes to form through-silicon vias (TSVs). The semiconductor chips are interconnected through the through-silicon vias. Alternatively, wire bonding may be used to interconnect the semiconductor chips.
According to wire bonding interconnection, semiconductor chips are configured to have different designs so that the positions of chip enable pads may be controlled. In this case, however, the semiconductor chips are produced by different processes, entailing considerable processing costs. Further, wire bonding is carried out after stacking of the semiconductor chips, rendering the processing procedure complicated. According to the stacking of semiconductor chips through through-silicon vias (TSVs), signal pads through which common signals of the semiconductor chips are applied and chip enable pads through which selection signals are applied have the same structure and arrangement and are connected in all semiconductor chips, making it impossible to substantially select the semiconductor chips.